Serial media independent interface

ABSTRACT

A 10/100Base-T MAC to PHY interface requiring only two wires (pins) per port, with two additional global wires: a clock wire (pin), and a synchronization wire (pin) represents a reduction in the number of pins associated with each port and is achieved by time-division multiplexing wherein each time-division multiplexed wire combines a plurality of definitions from the conventional 100Base-T interface specified by IEEE 802.3u (clause 22). As a result, each port has its own pair of associated time-division multiplexed wires (pins) and the addition of each port simply requires two additional wires. According to a preferred embodiment of the present invention, information normally transferred on sixteen wires in a conventional 100Base-T interface at 25 MHz is time-division multiplexed onto two wires (corresponding to two pins) that transfer data at 125 MHz, five times the speed of conventional interfaces. Importantly, this multiplexing is done on a port by port basis. Therefore, the number of pins required for a MAC to transceiver interface is two times the number of ports plus two instead of sixteen times the number of ports, and the addition of each additional port requires only two more wires (pins).

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/103,598,filed Mar. 20, 2002, titled SERIAL MEDIA INDEPENDENT INTERFACE, which isa continuation of application Ser. No. 09/088,956, filed Jun. 2, 1998,titled SERIAL MEDIA INDEPENDENT INTERFACE; the disclosures of which areincorporated herein by reference for all purposes.

BACKGROUND OF THE INVENTION

The present invention relates generally to network computing. Morespecifically, the present invention relates to methods and apparatusesfor connecting a system chip to a 10/100Base-T transceiver, and inparticular, to a reduced pin-count serial media independent interface.

In computer network systems there is typically a natural divisionbetween chips handling the physical layer, which is responsible fortransmitting data on the network, and the system chips, which performlogical operations with data transmitted on the network. Ethernet hubs,routers and switches are composed of multiple ports, and may begenerically referred to as multi-port Ethernet devices. Each port istypically composed of a system chip, which includes a media accesscontroller (“MAC”) layer, and a physical layer or “PHY.” Modernmulti-port Ethernet devices typically integrate multiple MACs into onesystem chip (MAC chip) as well as multiple PHYs into another chip (PHYchip). An interface is required on each chip to transfer signals betweenthe MACs and the PHYs.

IEEE standard 802.3u defines a media independent interface between a MAClayer and a PHY that includes 16 pins used for data and control. Asnoted above, in devices that include multiple ports that each have a MACand a PHY, it is common to implement multiple MACs on one chip andmultiple PHYs on another chip. If the standard MII, which includes 16pins for data and control, is used for each MAC and PHY on the MAC chipand the PHY chip, the number of pins required for each chip becomes verylarge as multiple MACs and PHYs are included on single chips.

For example, typical switches available today may offer 24 ports in asingle device. If all of the MACs were to be implemented on one chip andall of the PHYs were to be implemented on another chip then 384 pinswould be required just to provide the interface between the MACs and thePHYs of the two chips. Obviously this is impractical. Thus, therequirement of 16 pins for data and control in the standard MIIspecification adds to the expense of MAC and PHY interfaces both byincreasing the number of pins required on chips and by reducing thenumber of MACs and PHYs which may be combined on a single chip.

FIG. 1A is a block diagram illustrating a standard MAC to PHY interface.A MAC 100 is connected to a PHY 102 via a 16 wire MII. PHY 102 isconnected to a physical medium that transmits data over a network 104.MAC 100 is connected to a network device 106 in a device that is usingthe MAC and the PHY to communicate. The device may be a switch, arepeater, a hub or any other network device that includes ports forcommunication using the Ethernet 802.3u standard.

FIG. 1B is a block diagram illustrating the problem caused by the numberof pins required in the standard MII MAC to PHY interface. A MAC chip110 includes four MACs 112 a, 112 b, 112 c, and 112 d. Each of the fourMACs must have 16 pins on the outside of the chip so that it cancommunicate with a PHY according to the MII standard. Similarly, a PHYchip 120 includes four PHYs 122 a, 122 b, 122 c, 122 d. Each of the PHYsmust have 16 pins on the outside of the PHY chip so that it maycommunicate with the MAC via a standard 16 pin MII. Each PHY chip isalso connected to a physical medium that is used to communicate over anetwork 130.

It would be extremely useful if an alternative standard to the MIIstandard could be developed which would allow for communication betweena MAC and a PHY using a reduced number of lines between the MAC and thePHY. This would reduce the number of pins per MAC or PHY included on achip, reduce the cost of the chip, and allow more MACs or PHYs to beincluded on a single chip. An alternative interface to the MII shouldinclude all of the control signals and the same data capacity as the MIIso that such an interface could continue to be interoperable with allsystems that are intended to operate with an MII as described in IEEEstandard 802.3u.

FIG. 2 is a block diagram illustrating the functions of the sixteenlines specified in the MII standard. A MAC 200 is connected to a PHY 202using the 16 wire MII standard interface. The interface includes atransmit clock line 210 that provides a clock signal for clocking thetransmitted data. A transmit enable line 212 indicates when data isbeing transmitted on the transmit data lines. A transmit error line 214indicates an error should be forced onto the network. This line is used,for example, by repeaters to propagate errors that have been detected. Aset of four lines 215 are used to transmit data. Since the overall datatransfer rate between the MAC and the PHY is 100 MHz in a 100 Base-Tsystem, each of the four data wires transmits at 25 MHz.

The MII also includes a carrier sense line 215 which indicates that datais being either received or transmitted. In addition, a collision line220 is included which indicates that a collision has been detected,i.e., data is being both received and transmitted simultaneously. Areceive clock line 222 is used to provide a clock for clocking thereceived data. A set of four receive data lines 224 each transfer dataat 25 Mhz for an overall data rate of 100 MHz. A receive data valid line226 indicates that valid data is being transferred on the receive datalines. A receive error line 228 indicates when an error has beendetected in the received data, such as when an illegal symbol isdetected by the PHY.

An MII is commonly used with a 100Base-TX PHY, for example, where datais transmitted across the physical medium of the network from PHY to PHYat a data rate of 125 MHz. Bits of data are grouped into individualsymbols which include five bits each. The PHY receives each five bitsymbol and translates it into a four bit nibble of data. Thus, the fivebit symbol is used to transmit only four bits of data, with theremaining possible information states of the symbol used for errordetection or other purposes. When errors are detected by the PHY, theyare propagated to the MAC using the receive error line. Certain devices,such as repeaters, may use the transmit error line to propagate errorsto other devices on a network. It should be noted that the receive datavalid line differs from the carrier sense line in that the receive datavalid line does not go high as soon as data begins to be received.Instead, the receive data valid line goes high after an entire five bitsymbol corresponding to a nibble of valid data has been received anddecoded, and remains high after data has stopped being received betweenPHYs to allow decoding of all four bits of the nibble corresponding tothe last symbol transmitted. MIIs may also be used to connect a MAC to aPHY which uses another data transfer format, such as a 100Base-T4 PHY.

One approach to reducing the number of pins required for the MAC to PHYinterface has been proposed by the Reduced Media Independent Interface™(RMII™) consortium. The RMII provides a six pin interface between a MACand a PHY. In addition to the six wires required for each MAC to PHYinterface, a single synchronous clock signal is provided for bothtransmit data sent from the MAC to the PHY and the receive data sentfrom the PHY to the MAC. In the six pin RMII, two pins are used totransmit data and two pins are used to receive data. Each of the datatransmit and the data receive lines runs at 50 Mhz. This provides atotal bandwidth of 100 MHz for sending and a 100 MHz for receiving dataacross the MAC to PHY interface.

Thus, the RMII reduces the number of pins required to transmit andreceive data from eight to four by doubling the clock speed of the datalines. The RMII reduces the eight pins required to send the remainingsix control signals to only two pins by combining certain controlsignals and deriving other control signals in the manner describedbelow. The transmit clock and the receive clock lines are eliminated foreach individual MAC to PHY interface because a single synchronous clockis used for all of the interfaces on a single chip. The remaining sixcontrol signals are combined and derived from only two control lines asis described below.

The carrier sense and receive data valid control signals are combined ona single line by the RMII. As described above, the carrier sense signaldiffers from the receive data valid single in that the carrier sensesignal goes high as soon as the PHY begins to receive data. The receivedata valid signal goes high only after the PHY has received the firstcomplete symbol of data and decoded the first nibble of data. Also, thereceive data valid symbol remains high until the last nibblecorresponding to the last symbol has been transferred to the MAC. TheRMII combines the two signals into one on a single line as follows: thecombined signal asserts with carrier sense and remains asserted whileboth carrier sense and receive data valid are both asserted. The signalalternates between the asserted and deasserted state while carrier senseis not asserted, but receive data valid is still asserted, so thatcarrier sense and received data valid are time-division multiplexed. Thesignal becomes deasserted while both carrier sense and receive datavalid are deasserted.

On the second and last control line provided by the RMII, a transmitenable signal is provided. The collision signal is derived from thetransmit enable signal and the carrier sense portion of the carriersense data valid signal. When both are asserted, the RMII determinesthat a collision has occurred. The last two control signals, the receiveerror signal and the transmit error signal are transferred across theinterface by altering the data sent when an error is detected. When anillegal symbol is detected, the rest of the data is filled with aspecific data pattern such as alternating ones and zeros. When thespecific data pattern is read, then it is determined that an error hasoccurred. There is a finite probability that good data may match thespecific data pattern causing the MACs to determine that an error hasoccurred when, in fact, no error has occurred. However, the RMII isdesigned so that the probability of such mistakes occurring isacceptably small to the system designers.

It should also be noted that the IEEE MII specification requiresbackward compatibility with a 10base-T Ethernet interface so that datamay be transferred between the MAC and the PHY at either 100 MHz or 10MHz. When data is transmitted at 10 MHz, then each bit is repeated tentimes so that the 10 MHz data may be recovered by sampling every tenthbit. It is necessary, therefore, to indicate to the MAC or the PHYwhether data is being transmitted at 100 MHz or 10 MHz so that propersampling of the data may be implemented. The RMII accomplishesdetermining the correct data rate by using an out-of-band communicationbetween the MAC and the PHY. The MAC queries a designated PHY registerusing the MII management bus to determine the selected data rate. Itwould be useful if an alternative to this out-of-band communicationcould be developed since the out-of-band communication is slow and thereis a possibility that the out-of-band communication may not beaccomplished before data is transmitted.

Accordingly, it would be useful if the number of wires interfacing a10/100Base-T MAC and PHY could be even further reduced to less than sixwires. Furthermore, it would be useful if an in-band data ratecommunication between the MAC and the PHY could be developed.

SUMMARY OF THE INVENTION

The present invention addresses this problem by providing a 10/100Base-TMAC to PHY interface requiring only two wires (pins) per port, with twoadditional global wires: a clock wire (pin), and a synchronization wire(pin). This reduction in the number of pins associated with each port isachieved by time-division multiplexing wherein each time-divisionmultiplexed wire combines a plurality of definitions from theconventional 100Base-T interface specified by IEEE 802.3u (clause 22).As a result, each port has its own pair of associated time-divisionmultiplexed wires (pins) and the addition of each port simply requirestwo additional wires. According to a preferred embodiment of the presentinvention, information normally transferred on sixteen wires in aconventional 100Base-T interface at 25 MHz is time-division multiplexedonto two wires (corresponding to two pins) that transfer data at 125MHz, five times the speed of conventional interfaces. Importantly, thismultiplexing is done on a port by port basis. Therefore, the number ofpins required for a MAC to transceiver interface is two times the numberof ports plus two instead of sixteen times the number of ports, and theaddition of each additional port requires only two more wires (pins).Moreover, the present invention provides for in-band data ratedetermination.

In one aspect, the present invention provides a multi-port 10/100Base-TEthernet device. The device includes a MAC chip, a PHY chip, and aninterface connecting the MAC and PHY chips. The interface includes twotime-division multiplexed wires per port, each time-division multiplexedwire conveying time-division multiplexed signals having differentdefinitions, and two global wires conveying clock and synchronizationpulse signals for up to all of the ports.

In another aspect, the present invention provides a 10/100Base-T MAC toPHY interface. The interface includes two time-division multiplexedwires for each port serviced by the interface, each time-divisionmultiplexed wire conveying time-division multiplexed signals havingdifferent definitions, and two global wires conveying clock andsynchronization pulse signals for one or more ports.

In a further aspect, the present invention provides a method ofinterfacing a MAC to a PHY in a 10/100Base-T Ethernet device. The methodinvolves conveying a first plurality of time-division multiplexedsignals having different definitions from a MAC to a PHY over a transmitwire, and a second plurality of time-division multiplexed signals havingdifferent definitions from the PHY to the MAC over a receive wire. Inaddition, the method involves conveying a clock signal to the MAC andPHY over a global clock wire, and a synchronization pulse signal to theMAC and PHY over a global synchronization pulse wire.

In still a further aspect, the present invention provides a method ofinterfacing a plurality of MACs in a 10/100Base-T Ethernet device. Themethod involves conveying a first plurality of time-division multiplexedsignals having different definitions from a first MAC to a second MACover one wire, and a second plurality of time-division multiplexedsignals having different definitions from the second MAC to the firstMAC over another wire. In addition, the method involves conveying aclock signal to the MACs over a global clock wire, and a synchronizationpulse signal to the MACs over a global synchronization pulse wire.

It should be appreciated that the present invention can be implementedin numerous ways, including as a device, a process, or a system. Someinventive embodiments of the present invention are described below.

These and other features and advantages of the present invention will bepresented in more detail in the following specification of the inventionand the accompanying figures which illustrate by way of example theprinciples of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the followingdetailed description in conjunction with the accompanying drawings,wherein like reference numerals designate like structural elements, andin which:

FIG. 1A depicts a block diagram illustrating a standard 10/100Base-T MACto PHY interface.

FIG. 1B depicts a block diagram illustrating the problem caused by thenumber of pins required in the standard MII 10/100Base-T MAC to PHYinterface.

FIG. 2 depicts a block diagram illustrating the functions of the sixteenlines specified in the MII standard.

FIG. 3 depicts an implementation of a serial media independent interface(SMII) in accordance with a preferred embodiment of the presentinvention.

FIG. 4 depicts a sequence diagram illustrating the receive path and thesynchronicity between the interface clock, synchronization pulse, andthe receive signals, for a 10/100Base-T MAC to PHY SMII in accordancewith a preferred embodiment of the present invention.

FIG. 5 depicts a sequence diagram illustrating the transmit path and thesynchronicity between the interface clock synchronization pulse and thetransmit signals, for a 10/100Base-T MAC to PHY SMII in accordance witha preferred embodiment of the present invention.

FIG. 6 depicts a flow diagram of a method of interfacing a 10/100Base-TMAC to PHY in accordance with a preferred embodiment of the presentinvention.

FIG. 7 depicts a block diagram illustrating how an SMII in accordancewith the present invention may be used for full duplex MAC to MACcommunication.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to a preferred embodiment of theinvention. An example of the preferred embodiment is illustrated in theaccompanying drawings. While the invention will be described inconjunction with that preferred embodiment, it will be understood thatit is not intended to limit the invention to one preferred embodiment.On the contrary, it is intended to cover alternatives, modifications,and equivalents as may be included within the spirit and scope of theinvention as defined by the appended claims. In the followingdescription, numerous specific details are set forth in order to providea thorough understanding of the present invention. The present inventionmay be practiced without some or all of these specific details. In otherinstances, well known process operations have not been described indetail in order not to unnecessarily obscure the present invention.

The present invention provides a 10/100Base-T MAC to PHY interfacerequiring only two wires (pins) per port, with two additional globalwires: a clock wire (pin), and a synchronization wire (pin). Thisreduction in the number of pins associated with each port is achieved bytime-division multiplexing wherein each time-division multiplexed wirecombines a plurality of definitions from the conventional 100Base-Tinterface specified by IEEE 802.3u (clause 22). As a result, each porthas its own pair of associated time-division multiplexed wires (pins)and the addition of each port simply requires two additional wires.According to a preferred embodiment of the present invention,information normally transferred on sixteen wires in a conventional100Base-T interface at 25 MHz is time-division multiplexed onto twowires (corresponding to two pins) that transfer data at 125 MHz, fivetimes the speed of conventional interfaces. Importantly, thismultiplexing is done on a port by port basis. Therefore, the number ofpins required for a MAC to transceiver interface is two times the numberof ports plus two instead of sixteen times the number of ports, and theaddition of each additional port requires only two more wires (pins).

An implementation of a serial media independent interface (“SMII”) inaccordance with a preferred embodiment of the present invention isillustrated in a block diagram in FIG. 3. The figure shows a multi-port10/100Base-T Ethernet device 300, for example, a switch, router or hub.The device 300 has eight ports each composed of a MAC and a PHY. In thisparticular embodiment, the MACs and PHYs composing the ports are locatedon an 8-port MAC chip 302, and two quad (4-port) PHY chips 304 and 306,respectively.

According to a preferred embodiment of the present invention, thetransmit data and transmit control (transmit enable and transmit error)signals are multiplexed on one wire for each port. For example, as shownin FIG. 3, transmit lines 308 and 310 represent four wires each, one foreach port on the device 300. Similarly, the receive data and receivecontrol (receive data valid, carrier sense, and receive error) signalsare multiplexed on a second wire for each port, for example receivelines 312 and 314 represent four wires each, one for each port on thedevice 300.

Of the remaining signals, the transmit clock signal is replaced by aglobal interface clock line (pin/wire) 320 which provides a globalsynchronized clock signal for from a plurality of ports to all the portson the multi-port 10/100Base-T Ethernet device. The receive clock signalis handled in such a way that it does not require connection via a wire,as described further below. As noted previously, an additional signal isused in this invention, that being a synchronization pulse signal, whichlike the global interface clock signal, has its own dedicated globalsynchronization pulse line (pin/wire) 324 tied to a plurality of portsup to all of the ports on a multi-port 10/100Base-T Ethernet device.

Therefore, the number of pins required for a MAC to transceiverinterface using SMII is two times the number of ports plus two, insteadof sixteen times the number of ports, as in conventional MII, or sixtimes the number of ports plus one, as in the RMII. Moreover, the SMIIprovides for in-band data rate (either 10 or 100 MHz) determination, andthe addition of each additional port requires only two more wires(pins).

The SMII Receive Path

FIG. 4 depicts a sequence diagram illustrating the receive path and thesynchronicity between the interface clock synchronization pulse and thereceive signals, for a 10/100Base-T MAC to PHY SMII in accordance with apreferred embodiment of the present invention. Data is preferablyconveyed at one bit per 125 clock cycle. A SMII in accordance with apreferred embodiment of the present invention can handle different datarates, for example, 10 and 100 MBit/s. In 100 MBit/s mode, each segmentrepresents a new byte of data. In 10 MBit/sec mode, each segment isrepeated ten times so every ten segments represents a new byte of data.The MAC samples one of every ten segments when data is sent in 10MBit/sec mode. The MAC determines the data rate from inter-frame statusbits conveyed on the receive wire, as further described below.

The top-most line 402 in the sequence diagram 400 represents a 125 MHzglobal clock. As noted above, the global clock signal is conveyed on aglobal wire to a plurality of ports up to all of the ports on amulti-port 10/100Base-T Ethernet device. The data on the wires of theMAC to PHY interface is sampled and/or driven on the up stroke of eachcycle of the clock signal, as indicated by the vertical lines 403 of thesequence diagram 400.

The second line 404 on FIG. 4 represents the synchronization pulsesignal, which is asserted one out of every ten cycles of the globalclock 402 (every ten clocks), in order to synchronize the MAC to thedata stream. The synchronization pulse signal is an additional signalnot found among the signals conveyed by a conventional MII. As in theRMII, the purpose of the synchronization pulse in an SMII in accordancewith the present invention is to signal the end of each cycle of signals(segment). The synchronization pulse is high during the conveyance ofthe first of each segment of signals, as described further below. Thesynchronization pulse signal 404 is also conveyed on a global wire to aplurality of ports up to all of the ports on a multi-port 10/100Base-TEthernet device.

The third line 406 on FIG. 4 represents the receive signal. Since theglobal interface clock speed is five times that of the transmit andreceive clocks of a conventional MII, five times the information may beconveyed in the same given amount of time. The receive line 406 isdivided into “time slots” 408 which each represent one bit of data. Thereceive data and control signals are time-division multiplexed in 10 125MHz time slots (making up a 12.5 MHz segment) on a single receive wireper port in accordance with this preferred embodiment of the presentinvention. In this preferred embodiment, the first two time slots ofeach segment are dedicated to control signals, carrier sense (CRS) 410and receive data valid (RX_DV) 412, respectively. The remaining eightslots (RXD0-7) are dedicated to the conveyance of receive data signals.

A conventional MII conveys receive data at 100 MHz by using a 25 MHzclock and four receive data wires. It takes a wire operating at 25 MHz40 ns to convey 1 bit of data; in MII, four 25 MHz wires convey 4 bitsof receive data in 40 ns (1 bit per 10 ns). An SMII in accordance withthe present invention allows for the conveyance of data at the same rateas with conventional MII, but with many fewer wires. At 125 MHz it takesonly 8 ns to convey 1 bit of data. Therefore, the ten bits conveyed in asegment of receive signals using SMII, including 8 bits (1 byte;equivalent to two MII data nibbles) of receive data, take only 80 ns.Thus, SMII is able to sustain the MII's 1 bit per 10 ns rate ofconveying receive data, conveying all the information found on thereceive path of a conventional MII, while using only one wire for thepurpose.

In a preferred embodiment of the SMII, the two control bits (CRS andRX_DV) in the receive signal segment have the same purpose as thecommonly designated signals in MII, except that the signals are allsynchronous with the global clock. The SMII receive segment control bitscan also be used by the MAC to infer the meaning of the receive datasignals on a segment by segment basis by decoding the two control bits.For example, in the inter-frame period, when no receive data is beingconveyed on the interface, the RX_DV signal is 0. Since no valid data isbeing conveyed, the time slots (RXD0-7) normally allotted to receivedata when the RX_DV signal is high (1) may be used to convey statusinformation.

In one preferred embodiment, the RXD0 time slot is used to indicate areceive error (RX_ER) from the previous frame of data (where RXD0=1).The RXD1 time slot is used to indicate data rate; RXD1=0 indicates 10MBit/s, RXD1=1 indicates 100 MBit/s. Thus, the present inventionprovides in-band data rate communication. The RXD2 time slot is used toindicate the duplex mode; RXD2=0 indicates half duplex (MAC to PHYcommunication), RXD2=1 indicates full duplex (MAC to MAC communication).The RXD3 time slot is used to indicate the status of the network link(linktestpass); RXD3=0 indicates that the link is down, RXD3=1 indicatesthat the link is up. The RXD4 time slot is used to indicate the statusof the jabber signal (for 10Base-T compatibility); RXD4=0 indicates nojabber error, RXD4=1 indicates a jabber error. The RXD5 time slot isused to indicate the validity of the upper nibble of the last byte ofthe previous frame; RXD5=0 indicates the nibble is invalid, RXD5=1indicates the nibble is valid. In this preferred embodiment, the RXD6and RXD7 time slots are not used to convey status information. Ofcourse, other configurations and different status information may beconveyed using these principles in accordance with the presentinvention.

As noted above, the SMII of the present invention does not include areceive clock signal. Instead, the receive clock signal is handled, inaccordance with a preferred embodiment of the present invention, in amanner that does not require any additional wire between the MAC and PHYchips. With a conventional MII, the PHY passes both data and clocksignals to the MAC for each port. Each receive clock operates at anindependent frequency. In order to support the individual receive clocksin each conventional MAC chip, there is a dedicated receive clock wirein the MII interface between each MAC and PHY. Also, conventional MACchips may include an elasticity buffer which is large enough andoperates such that it may receive incoming data from the network (viathe PHY) and then transfer it to the upper layers using the devicesystem clock in such a manner that it does not empty or reach capacityduring the reception of a packet from the network.

In accordance with the present invention, the receive clock wire betweeneach MAC and PHY is eliminated by providing an elasticity buffer (FIFO)in the PHY instead of in the MAC. In this configuration, the PHY is ableto receive the data using a clock recovered from the data, and then passthe data to the MAC using the global clock. In order to send receivedata to the MAC synchronous to the global clock, the PHY passes the datathrough an elasticity FIFO to handle any difference between the globalclock rate and the clock rate at the packet source (10 MHz). Theelasticity FIFO on a PHY in accordance with the present invention shouldhas sufficient capacity, and is preferably operated so that it does notreach capacity nor empty during the reception of a packet. As such, thePHY may receive data using recovered clocks, allowing the buffer tobecome approximately half full, and then pass data to the MAC using theglobal clock, which will usually have a different phase and frequency.In this way the buffer never overflows or becomes empty over the courseof receiving and transmitting a packet of data, and no receive clockwire is necessary in the SMII.

The Ethernet specification (IEEE 802.3u) calls for packet data to bereferenced to a clock with a frequency tolerance of 100 ppm (0.01%).However, it is not uncommon to encounter Ethernet stations with clocksthat have frequency errors up to 0.1%. Thus, it is preferable that aFIFO be designed which allows communication with an end station that hasa frequency error of up to 0.1% instead of the 0.01% required by thestandard. Accordingly, in a preferred embodiment, the size of anelasticity FIFO with sufficient capacity so that the buffer neveroverflows or becomes empty over the course of receiving and transmittinga packet of data may be calculated as follows: FIFO size=2*(maximumframe in bits)*(end station error+local error). In one preferredembodiment, a PHY-based elasticity FIFO that is at least twenty-sevenbits long. The size of the FIFO is determined according to the followingformula: $\begin{matrix}{{{FIFO}\quad{size}} = {2*( {{maximum}\quad{frame}\quad{in}\quad{bits}} )*\begin{pmatrix}{{{end}\quad{station}\quad{error}} +} \\{{local}\quad{error}}\end{pmatrix}}} \\{= {2*( {1518*8} )*( {{0.1\%} + {0.01\%}} )}} \\{= {26.7\quad{{bits}.}}}\end{matrix}$

The elasticity FIFO is preferably allowed to fill to about the half waypoint before beginning valid data transfer. RXD and RX_DV signals arepassed through the elasticity FIFO. RX_ER is asserted if, during thereception of a frame, the FIFO overflows or underflows. The CRS signalis not passed through the elasticity FIFO; instead, the CRS signal isasserted (1) for the time that the PHY is receiving a frame of data.

The SMII Transmit Path

FIG. 5 depicts a sequence diagram illustrating the transmit path and thesynchronicity between the interface clock synchronization pulse and thetransmit signals, for a 10/100Base-T MAC to PHY SMII in accordance witha preferred embodiment of the present invention. Data and status areconveyed in substantially the same manner as described above withreference to the receive data path. That is, data is preferably conveyedat one bit per 125 MHz clock cycle. In 100 MBit/s mode, each segmentrepresents a new byte of data. In 10 MBit/sec mode, each segment isrepeated ten times so every ten segments represents a new byte of data.The PHY samples one of every ten segments when data is sent in 10MBit/sec mode. The MAC determines the data rate from inter-frame statusbits conveyed on the receive wire, as described above.

The top-most line 502 in the sequence diagram 500 represents a 125 MHzglobal clock. As noted above, the global clock signal is conveyed on aglobal wire to a plurality of ports up to all of the ports on amulti-port 10/100Base-T Ethernet device. The data on the wires of theMAC to PHY interface is read and/or driven on the up stroke of eachcycle of the clock signal, as indicated by the vertical lines 503 of thesequence diagram 500.

The second line 504 on FIG. 5 represents the synchronization pulsesignal, which, as noted above, is high for every ten cycles of theglobal clock 502 (every ten clocks), in order to synchronize the MAC tothe data stream. The MAC generates a synchronization pulse during theconveyance of the first of each segment of signals, as described furtherbelow. The synchronization pulse signal 504 is also conveyed on a globalwire to a plurality of ports up to all of the ports on a multi-port10/100Base-T Ethernet device.

The third line 506 on FIG. 5 represents the transmit path. As describedabove for the receive path, since the global interface clock speed isfive times that of the transmit and receive clocks of a conventionalMII, five times the information may be conveyed in the same given amountof time. The transmit line 506 is divided into “time slots” 408 whicheach represent one bit of data. The transmit data and control signalsare time-division multiplexed in 10 125 MHz time slots (making up a 12.5MHz segment) on a single transmit wire per port in accordance with thispreferred embodiment of the present invention. In this preferredembodiment, the first two time slots of each segment are dedicated tocontrol signals, transmit error (TX_ER) 510 and transmit enable (TX_EN)512. The remaining eight slots (TXD0-7) are dedicated to the conveyanceof transmit data signals.

A conventional MII conveys transmit data at 100 MHz by using a 25 MHzclock and four transmit data wires. It takes a wire operating at 25 MHz40 ns to convey 1 bit of data; in MII, four 25 MHz wires convey 4 bitsof transmit data in 40 ns (1 bit per 10 ns). As noted above in thedescription of the receive data path, an SMII in accordance with thepresent invention allows for the conveyance of data at the same rate aswith conventional MII, but with fewer wires. At 125 MHz it takes only 8ns to convey 1 bit of data. Therefore, the ten bits conveyed in asegment of transmit signals using SMII, including 8 bits (1 byte;equivalent to two MII data nibbles) of transmit data, take only 80 ns.Thus, SMII is able to sustain the MII's 1 bit per 10 ns rate ofconveying transmit data, conveying all the information found on thetransmit path of a conventional MII, while using only one wire for thepurpose.

It is generally not necessary to pass status information from the MAC tothe PHY because the PHY is able to detect the status. Therefore, in oneembodiment, no status information is passed using the transmit data linein a manner that status information is passed using the receive dataline. However, in other embodiments, this may be done if desired.

Collisions are detected when the transmit enable signal and the carriersense signal are both asserted. For this method of detecting collisionsto work, the PHY must ensure that CRS is not affected by its transmitpath. When both the transmit enable and carrier sense are asserted, thena collision has occurred.

FIG. 6 depicts a flow diagram of a method of interfacing a 10/100Base-TMAC to a PHY in accordance with a preferred embodiment of the presentinvention. It should be understood that this process flow is intended toillustrate the way in which signals are conveyed between MACs and PHYsin accordance with a preferred embodiment of the present invention, andnot to indicate a sequence of events. The various steps of the process600 may be occurring concurrently. The process 600 begins at 601, and ata step 602 time-division multiplexed transmit signals of differentdefinitions are conveyed from a MAC to a PHY over a transmit wire. At astep 604, time-division multiplexed receive signals of differentdefinitions are conveyed from the PHY to the MAC over a receive wire.

In addition, the MAC to PHY interface process 600 involves conveyingclock and synchronization signals on each of two global wires, asdescribed previously with reference to FIG. 3. At a step 606 of process600, a 125 MHz clock signal is conveyed to the MAC and the PHY over aglobal clock wire. At a step 608, a synchronization pulse signal isconveyed to the MAC and the PHY over a global synchronization pulsewire. Thus, the 10/100Base-T MAC to PHY interfacing may be accomplishedin accordance with the present invention using only 2 times (the numberof ports)+2 wires. The interfacing process ends at 610.

In addition to being used as a MAC to PHY interface, an SMII inaccordance with the present invention may also be used as a directconnection between two MACs. FIG. 7 is a block diagram illustrating howthe two wires of an SMII in accordance with the present invention may beconnected between a first MAC 700 and a second MAC 702. The receive lineand the transmit line of MAC 700 are connected to the transmit line andthe receive line of MAC 702, respectively. The receive and transmitsegments have nearly a bit to bit correspondence. The transmit enablesignal sent from one MAC can be interpreted as a receive data validsignal by the other MAC. The transmit segment does not include a bitthat signals carrier sense but for a MAC to MAC interface, the carriersense time slot can be defined to be deasserted. This is not a problemas long as both MACs are operating in full duplex mode.

Status information is included in the transmit path between frames whentransmit enable is 0. The first transmit data bit of the transmit line(TXD0) is used to force an error in a direct MAC to MAC connection, with1 indicating an error. The second bit of the transmit data line (TXD1)is used to indicate speed, with 0 indicating 10 MBits/s, and 1indicating 100 MBits/s. The third bit (TXD2) indicates duplex mode with1 indicating full duplex. The fourth bit (TXD3) indicates link statuswith 1 indicating that the link is up, and the fifth bit (TXD4)indicates jabber with a 0 indicating no jabber. In other embodiments,these conventions may be changed. When transmit enable is 1, then thetransmit data on the transmit line is interpreted as being an SMII databyte.

Thus, the present invention provides a two wire 10/100Base-T SMII usingtime-division multiplexed receive and transmit signals which can be usedto convey all of the data and control information transferred by thestandard IEEE MII interface. A common clock signal is used for both theMAC and the PHY and the time-division multiplexed segments aresynchronized using a synchronization pulse on the receive and thetransmit lines. Thus, the number of wires required for a 10/100Base-TMAC to PHY interface can be reduced, enabling more MACs or PHYs to beimplemented on a single chip.

Although the foregoing invention has been described in some detail forpurposes of clarity of understanding, it will be apparent that certainchanges and modifications may be practiced within the scope of theappended claims. It should be noted that there are many alternative waysof implementing both the process and apparatuses of the presentinvention. Accordingly, the present embodiments are to be considered asillustrative and not restrictive, and the invention is not to be limitedto the details given herein, but may be modified within the scope andequivalents of the appended claims.

1. A multi-port Ethernet device, comprising: a MAC chip having one ormore ports; a PHY chip having one or more ports; and a 10/100Base-Tinterface connecting said MAC and PHY chips, said interface comprising,two time-division multiplexed wires per port on each chip, eachtime-division multiplexed wire configured for conveying time-divisionmultiplexed signals having different definitions, and two global wiresconfigured for conveying clock and synchronization pulse signals for upto all of the ports on each chip.
 2. The Ethernet device of claim 1,wherein said 10/100Base-T interface is configured to convey all requiredsignals between said MAC chip and said PHY chip with 2n+2 wires, where nis the number of ports on each chip connected by the interface.
 3. TheEthernet device of claim 1, wherein said two time-division multiplexedwires comprise a transmit wire and a receive wire.
 4. The Ethernetdevice of claim 3, wherein said transmit wire is configured to conveytransmit enable, transmit data, and transmit error signals in a segmentfrom said MAC chip to said PHY chip.
 5. The Ethernet device of claim 4,wherein said receive wire is configured to convey receive data valid,carrier sense, and receive data signals in a segment from said PHY chipto said MAC chip.
 6. The Ethernet device of claim 5, wherein saidtransmit and receive wires are configured to convey 8 bits of data persegment.
 7. The Ethernet device of claim 1, wherein said clock signalhas a frequency of about 125 MHz.
 8. The Ethernet device of claim 1,wherein, in operation, said time-division multiplexed signals areconveyed on said time-division multiplexed wires in about 12.5 MHz timeslots.
 9. The Ethernet device of claim 1, wherein, in operation, saidsynchronization pulse is asserted one out of every ten clocks.
 10. TheEthernet device of claim 1, wherein said PHY chip comprises anelasticity FIFO.
 11. The Ethernet device of claim 10, wherein thecapacity of said elasticity FIFO is calculated as follows:FIFO size=2*(maximum frame in bits)*(end station error+local error). 12.A 10/100Base-T interface connecting MAC and PHY chips each having one ormore ports, said interface comprising: two time-division multiplexedwires per port on each chip, each time-division multiplexed wireconfigured for conveying time-division multiplexed signals havingdifferent definitions, and two global wires configured for conveyingclock and synchronization pulse signals for up to all of the ports oneach chip.
 13. The interface of claim 12, wherein said 10/100Base-Tinterface is configured to convey all required signals between said MACchip and said PHY chip with 2n+2 wires, where n is the number of portson each chip connected by the interface.
 14. The interface of claim 12,wherein said two time-division multiplexed wires comprise a transmitwire and a receive wire.
 15. The interface of claim 14, wherein saidtransmit wire conveys a transmit enable, transmit data, and transmiterror signals in a segment from said MAC chip to said PHY chip.
 16. Theinterface of claim 15, wherein said receive wire conveys receive datavalid, carrier sense, and receive data signals in a segment from saidPHY chip to said MAC chip.
 17. The interface of claim 16, wherein saidtransmit and receive wires are configured to convey 8 bits of data persegment.
 18. The interface of claim 12, wherein said clock signal has afrequency of about 125 MHz.
 19. The interface of claim 12, wherein, inoperation, said time-division multiplexed signals are conveyed on saidtime-division multiplexed wires in about 12.5 MHz time slots.
 20. Theinterface of claim 12, wherein, in operation, said synchronization pulseis asserted one out of every ten clocks.
 21. A method of interfacing aMAC chip to a PHY chip in an Ethernet device, comprising: conveying afirst plurality of time-division multiplexed signals having differentdefinitions from a MAC chip to a PHY chip over a 10/100Base-T transmitwire; conveying a second plurality of time-division multiplexed signalshaving different definitions from the PHY chip to the MAC chip over a10/100Base-T receive wire; conveying a clock signal to said MAC chip andsaid PHY chip over a global clock wire; and conveying a synchronizationpulse signal to said MAC chip and said PHY chip over a globalsynchronization pulse wire.
 22. The method of claim 21, wherein said10/100Base-T interface conveys all required signals between said MACchip and said PHY chip with 2n+2 wires, where n is the number of portson each chip connected by the interface.
 23. The method of claim 21,wherein said transmit wire conveys a transmit enable, transmit data, andtransmit error signals in a segment from said MAC chip to said PHY chip.24. The method of claim 23, wherein said receive wire conveys receivedata valid, carrier sense, and receive data signals in a segment fromsaid PHY chip to said MAC chip.
 25. The method of claim 24, wherein saidtransmit and receive wires convey 8 bits of data per segment.
 26. Themethod of claim 21, wherein said clock signal has a frequency of about125 MHz.
 27. The method of claim 21, wherein said time-divisionmultiplexed signals are conveyed on said time-division multiplexed wiresin about 12.5 MHz time slots.
 28. The method of claim 21, wherein saidsynchronization pulse is asserted one out of every ten clocks.
 29. Themethod of claim 21, wherein said PHY chip comprises an elasticity FIFO.30. The method of claim 29, wherein the capacity of said elasticity FIFOis calculated as follows:FIFO size=2*(maximum frame in bits)*(end station error+local error). 31.A method of interfacing a plurality of MAC chips in a 10/100Base-TEthernet device, comprising: conveying a first plurality oftime-division multiplexed signals having different definitions from afirst MAC chip to a second MAC chip over a first 10/100Base-T wire;conveying a second plurality of time-division multiplexed signals havingdifferent definitions from the second MAC chip to the first MAC chipover a second 10/100Base-T wire; conveying a clock signal to said firstand second MAC chips over a global clock wire; and conveying asynchronization pulse signal to said first and second MAC chips over aglobal synchronization pulse wire.
 32. A multi-port Ethernet device,comprising: a MAC chip having one or more ports; a PHY chip having oneor more ports; and means for conveying all signals required for a10/100Base-T interface between said MAC chip and said PHY chip with 2n+2wires, where n is the number of ports on each chip connected by theinterface.
 33. A multi-port Ethernet media access control layer chip,comprising: a 10/100Base-T interface for connecting said media accesscontrol layer chip with a physical layer chip, said interfacecomprising, two time-division multiplexed pins per port on said mediaaccess control layer chip, each time-division multiplexed pin configuredfor conveying time-division multiplexed signals having differentdefinitions, and two global pins configured for conveying clock andsynchronization pulse signals for up to all of the ports on said mediaaccess control layer chip.
 34. The media access control layer chip ofclaim 33, wherein said 10/100Base-T interface is configured to conveyall required signals between said MAC chip and said PHY chip with 2n+2wires, where n is the number of ports on each chip connected by theinterface.
 35. The media access control layer chip of claim 33, whereinsaid two time-division multiplexed pins comprise a transmit pin and areceive pin.
 36. The media access control layer chip of claim 35,wherein said transmit pin is configured to convey transmit enable,transmit data, and transmit error signals in a segment from said mediaaccess control layer chip to a physical layer chip.
 37. The media accesscontrol layer chip of claim 36, wherein said receive pin is configuredto convey receive data valid, carrier sense, and receive data signals ina segment from a physical layer chip to said media access control layerchip.
 38. The media access control layer chip of claim 37, wherein saidtransmit receive pins are configured to convey 8 bits of data persegment.
 39. The media access control layer chip of claim 33, whereinsaid clock signal has a frequency of about 125 MHz.
 40. The media accesscontrol layer chip of claim 33, wherein, in operation, saidtime-division multiplexed signals are conveyed on said time-divisionmultiplexed pins in about 12.5 MHz time slots.
 41. The media accesscontrol layer chip of claim 33, wherein, in operation, saidsynchronization pulse is asserted one out of every ten clocks.
 42. Amulti-port Ethernet physical layer chip, comprising: a 10/100 Base-Tinterface for connecting said physical layer chip with a media accesscontrol layer chip, said interface comprising, two time-divisionmultiplexed pins per port on said physical layer chip, eachtime-division multiplexed pin configured for conveying time-divisionmultiplexed signals having different definitions, and two global pinsconfigured for conveying clock and synchronization pulse signals for upto all of the ports on said physical layer chip.
 43. The physical layerchip of claim 42, wherein said 10/100Base-T interface is configured toconvey all required signals between said MAC chip and said PHY chip with2n+2 wires, where n is the number of ports on each chip connected by theinterface.
 44. The physical layer chip of claim 42, wherein said twotime-division multiplexed pins comprise a transmit pin and a receivepin.
 45. The physical layer chip of claim 44, wherein said transmit pinis configured to convey transmit enable, transmit data, and transmiterror signals in a segment from a media access control layer chip tosaid physical layer chip.
 46. The physical layer chip of claim 45,wherein said receive pin is configured to convey receive data valid,carrier sense, and receive data signals in a segment from said physicallayer chip to a media access control layer chip.
 47. The physical layerchip of claim 46, wherein said transmit and receive pins convey 8 bitsof data per segment.
 48. The physical layer chip of claim 42, whereinsaid clock signal has a frequency of about 125 MHz.
 49. The physicallayer chip of claim 42, wherein, in operation, said time-divisionmultiplexed signals are conveyed on said time-division multiplexed pinsin about 12.5 MHz time slots.
 50. The physical layer chip of claim 42,wherein, in operation, said synchronization pulse is asserted one out ofevery ten clocks.
 51. The physical layer chip of claim 42, wherein saidphysical layer chip further comprises an elasticity FIFO.
 52. Thephysical layer chip of claim 51, wherein the capacity of said elasticityFIFO is calculated as follows:FIFO size=2*(maximum frame in bits)*(end station error+local error).